APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION

20240160351

18/504362

November 08, 2023

Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.

Micron Technology, Inc. (Boise, ID, US)

1. A method comprising: writing a value to a mode register of a memory device to enable a first mode or a second mode; performing a first write operation to a memory bank of the memory device, the first write operation including writing data and metadata to the memory bank of the memory; after performing the first write operation waiting at least a first amount of time before performing a second write operation to the memory bank when the device is in the first mode; and after performing the first write operation waiting at least a second amount of time before performing the second write operation to the memory bank when the device is in the first mode.

2. The method of claim 1, wherein the first amount of time includes a latency time tCCD_L_WR and the second amount of time includes a latency time less than tCCD_L_WR.

3. The method of claim 1, further comprising writing the data along four data terminals as part of the first write operation or the second write operation.

4. The method of claim 1, wherein the first write operation or the second write operation includes writing sixty-four data bits and four metadata bits to the memory array.

5. The method of claim 1, wherein the first write operation includes generating a column address and providing the column address to the memory device, wherein the column address is generated based on a range of column select signal values and wherein the range is less than all of the possible column select signal values.

6. The method of claim 1, further comprising: performing a read operation including reading the data and the metadata from the memory array; and receiving a signal from the memory device which indicates a double bit error was detected in the data and the metadata as part of the first mode or the second mode.

7. The method of claim 1, further comprising: writing a value to the mode register to enable a third mode of the memory device; and after performing the first write operation waiting at least a third amount of time before performing the second write operation to the memory bank when the device is in the third mode, wherein the third amount of time is longer than the first or the second amount of time.

8. The method of claim 7, wherein the first amount of time includes a latency time tCCD_L_WR, the second amount of time does includes a latency time less than tCCD_L_WR, and the third amount of time includes a latency time of two tCCD_L_WR.

9. A system comprising: a memory device comprising: a mode register configured to store a value, wherein based on the value the memory device operates in a first mode or a second mode; a first column plane comprising a first plurality of bit lines; a second column plane comprising a second plurality of bit lines; an input/output circuit configured to receive data and metadata as part of a write operation, wherein the data is written to the first plurality of bit lines and the metadata is written to selected ones of the second plurality of bit lines as part of the write operation; a logic decoder configured to provide a first write enable signal which activates the selected ones and the non-selected ones of the second plurality of bit lines in the first mode or a second write enable signal which activates the selected ones but not the non-selected ones of the second plurality of bit lines in the second mode. a controller configured to write the value to the mode register to set the memory in the first or the second operational mode.

10. The system of claim 9, wherein the selected ones of the second plurality of bit lines are even or odd ones of the second plurality of bit lines and the non-selected ones of the second plurality of bit lines are odd or even ones of the second plurality of bit lines.

11. The system of claim 9, wherein the controller is configured to provide a column address as part of the write operation, and wherein the column decoder is configured to decode the column address into a column select signal which has a same value for the first and the second plurality of bit lines.

12. The system of claim 9, wherein the first column plane is a data column plane and the second column plane is an extra column plane.

13. The system of claim 9, wherein the controller is configured to wait a first amount of time after the write operation before performing a second write operation to the memory bank when the device is in the first mode or wait a second amount of time after the write operation before performing a second write operation to the memory bank when the device is in the second mode.

14. The system of claim 9, wherein the memory device further comprises a global column repair (GCR) column plane comprising a plurality of redundant bit lines, wherein if the second plurality of bit lines are repaired to the plurality of redundant bit lines then the second write enable signal is provided to the plurality of redundant bit lines in the second mode.

15. A method comprising: writing a value to a mode register of a memory device to enable a first mode or a second mode; writing data and metadata to a memory array of the memory device and providing a column address as part of a write operation to a memory bank; activating a first write enable signal or a second write enable signal responsive to the write operation, wherein the second write enable signal has a first state or a second state based on a column address; writing data to selected bit lines in a first column plane responsive to the first write enable signal; and writing metadata to a first portion or a second portion of selected bit lines in a second column plane responsive to the state of the second write enable signal.

16. The method of claim 15, further comprising waiting a first amount of time after the write operation before performing a second write operation to the memory bank when the device is in the first mode or waiting a second amount of time after the write operation before performing a second write operation to the memory bank when the device is in the second mode.

17. The method of claim 16, wherein the first amount of time includes a latency time of tCCD_L_WR and the second amount of time includes an extra latency time of less than tCCD_L_WR.

18. The method of claim 15, wherein the first portion is even ones of the selected bit lines and the second portion is odd ones of the selected bit lines.

19. The method of claim 15, further comprising: generating parity bits based on the data and the metadata; and writing the parity bits to selected bit lines in a third column plane.

20. The method of claim 15, further comprising selecting a first portion or a second portion of a plurality of column planes based on a column plane select bit of the column address, wherein the first column plane is in the first portion or the second portion and wherein the second column plane is not in the first portion or the second portion.

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