- Document Number:
20250089323
- Appl. No:
18/827272
- Application Filed:
September 06, 2024
- Abstract:
A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.
- Claim:
1. A vertical power semiconductor device, comprising: a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface, the SiC semiconductor body including a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection; a source or emitter electrode; and a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, the gate interconnection, or the gate pad, wherein a value of a conduction band offset at the first interface ranges from 1.0 eV to 2.5 eV.
- Claim:
2. The vertical power semiconductor device of claim 1, wherein a portion of the source or emitter electrode at the first interface comprises at least one of aluminum, copper, titanium, nickel, molybdenum, tungsten, or alloys thereof.
- Claim:
3. The vertical power semiconductor device of claim 1, wherein a portion of the first interlayer dielectric at the first interface comprises a high-k material.
- Claim:
4. The vertical power semiconductor device of claim 3, wherein the high-k material is at least one of an oxide of aluminum, an oxide of zirconium, a nitride of aluminum, an oxide of hafnium, an oxide of yttrium, an oxide of silicon nitride, silicon nitride, or aluminum nitride.
- Claim:
5. The vertical power semiconductor device of claim 1, wherein the gate structures comprise a gate dielectric arranged between the gate electrode and the SiC semiconductor body, and a portion of the gate dielectric at a channel interface to the SiC semiconductor body is a high-k dielectric.
- Claim:
6. The vertical power semiconductor device of claim 1, wherein the conduction band offset at the first interface of the first interlayer dielectric is smaller than a conduction band offset at a channel interface to the SiC semiconductor body.
- Claim:
7. The vertical power semiconductor device of claim 1, wherein the gate structures comprise at least one of planar gate structures or trench gate structures, and at least a part of the second interface is arranged in the transistor cell area, the part of the second interface being directly opposite to the first interface.
- Claim:
8. The vertical power semiconductor device of claim 1, wherein at least a part of the second interface is arranged in the interconnection area, the part of the second interface being directly opposite to the first interface.
- Claim:
9. The vertical power semiconductor device of claim 8, wherein the part of the second interface is arranged directly opposite to a part of the source or emitter electrode having two edges a bottom side that turn into one another at an angle equal to or smaller than 90°.
- Claim:
10. The vertical power semiconductor device of claim 1, wherein at least a part of the second interface of the first interlayer dielectric is arranged in the interconnection area, the part of the second interface being directly opposite to the first interface along a first lateral direction, wherein a part of the first interlayer dielectric is arranged laterally between a source or emitter line of the source or emitter electrode and the gate interconnection.
- Claim:
11. The vertical power semiconductor device of claim 1, wherein the gate interconnection includes a gate resistor having a gate resistance in the range from 5Ω to 20Ω.
- Claim:
12. The vertical power semiconductor device of claim 1, further comprising a second interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface of the second interlayer dielectric is larger than the conduction band offset at the first interface of the first interlayer dielectric.
- Claim:
13. The vertical power semiconductor device of claim 12, wherein the second interlayer dielectric comprises an oxide of silicon.
- Claim:
14. The vertical power semiconductor device of claim 12, wherein the conduction band offset at the first interface of the second interlayer dielectric is by 0.5 eV to 1.5 eV larger than the conduction band offset at the first interface of the first interlayer dielectric.
- Claim:
15. A vertical power semiconductor device, comprising: a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface, the SiC semiconductor body including a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection; a source or emitter electrode; and a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, the gate interconnection, or the gate pad, wherein a value of a valence band offset at the second interface ranges from 1.0 eV to 2.5 eV.
- Claim:
16. The vertical power semiconductor device of claim 15, further comprising a second interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, the gate interconnection, or the gate pad, wherein a valence band offset at the second interface of the second interlayer dielectric is larger than the valence band offset at the second interface of the first interlayer dielectric.
- Claim:
17. The vertical power semiconductor device of claim 16, wherein the second interlayer dielectric comprises an oxide of silicon.
- Claim:
18. The vertical power semiconductor device of claim 16, wherein a value of the valence band offset at the second interface of the second interlayer dielectric is by 0.5 eV to 3.0 eV larger than a value of the valence band offset at the second interface of the first interlayer dielectric.
- Claim:
19. (canceled)
- Claim:
20. (canceled)
- Current International Class:
01; 01; 01; 01
- Accession Number:
edspap.20250089323
Processing Request
No Comments.