Semiconductor device and method for forming the same

12272,734

17/461793

August 30, 2021

A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu, TW); NATIONAL TAIWAN UNIVERSITY (Taipei, TW)

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu, TW), National Taiwan University (Taipei, TW)

1. A method for forming a semiconductor device, comprising: forming a semiconductor strip extending upwardly from a substrate; forming a fin structure having a sacrificial layer over the semiconductor strip and a stack of alternating first and second semiconductor layers over the sacrificial layer; forming an isolation dielectric laterally surrounding the semiconductor strip; forming a hard mask layer across the fin structure, such that the hard mask layer has a first portion wrapping around the stack, a second portion on a sidewall of the sacrificial layer, and a third portion extending on a top surface of the isolation dielectric; forming a dummy gate structure over the hard mask layer and across the fin structure; patterning the dummy gate structure to form an opening exposing the third portion of the hard mask layer, wherein from a top view, the opening does not overlap the fin structure; removing the second and third portions of the hard mask layer through the opening to expose the sidewall of the sacrificial layer; after removing the second and third portions of the hard mask layer, removing the sacrificial layer through the opening to form a space below the stack of the alternating first and second semiconductor layers; forming an isolation layer filling up the space through the opening, such that the isolation layer is sandwiched between the substrate and the stack of the alternating first and second semiconductor layers; after forming the isolation layer, removing the first portion of the hard mask layer and the patterned dummy gate structure; after removing the first portion of the hard mask layer and the patterned dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended over the isolation layer; and forming a gate structure to surround each of the suspended second semiconductor layers.

2. The method of claim 1 , wherein the sacrificial layer and the first semiconductor layer are made of a germanium-containing material, and the sacrificial layer has a different germanium atomic percentage concentration than the first semiconductor layer.

3. The method of claim 1 , wherein the hard mask layer is made of a carbon-containing material.

4. The method of claim 1 , further comprising: etching portions of the stack of the alternating first and second semiconductor layers that extend laterally beyond the hard mask layer and the dummy gate structure to expose portions of the sacrificial layer prior to patterning the dummy gate structure; and forming a plurality of source/drain structures over the exposed portions of the sacrificial layer on either side of the stack of the alternating first and second semiconductor layers.

5. A method for forming a semiconductor device, comprising: forming a semiconductor strip extending upwardly from a substrate, wherein from a top view, the semiconductor strip has a length extending along a first direction; forming a sacrificial layer over the semiconductor strip; forming a stack of alternating channel layers and semiconductor layers above the sacrificial layer, wherein from the top view, the channel layers and the semiconductor layers extend in the first direction, and from a cross-sectional view, the channel layers and the semiconductor layers are arranged in a second direction substantially perpendicular to a top surface of the substrate; forming an isolation dielectric laterally surrounding the semiconductor strip; forming a hard mask layer extending across the stack and the sacrificial layer, such that the hard mask layer has a first portion wrapping around the stack, a second portion on a sidewall of the sacrificial layer, and a third portion extending on a top surface of the isolation dielectric; forming a dummy gate structure over the hard mask layer and extending across the stack and the sacrificial layer; forming a pair of source/drain structures above the semiconductor strip and on either side of the channel layers; patterning the dummy gate structure to form an opening exposing the third portion of the hard mask layer, wherein from the top view, the opening does not overlap the stack; removing the second and third portions of the hard mask layer through the opening to expose the sidewall of the sacrificial layer; removing the sacrificial layer through the opening to form a space between the semiconductor strip and the stack and between the semiconductor strip and one of the source/drain structures; forming an isolation layer in the space through the opening; after forming the isolation layer, removing the patterned dummy gate structure, the first portion of the hard mask layer, and the semiconductor layers; and forming a gate structure surrounding each of the channel layers.

6. The method of claim 5 , wherein the isolation layer is in direct contact with the gate structure.

7. The method of claim 5 , wherein the gate structure comprises a high-k dielectric layer lining a sidewall and a top surface of the isolation layer.

8. The method of claim 5 , wherein the isolation layer extends past an interface between a longest side of the semiconductor strip and the isolation dielectric.

9. The method of claim 8 , wherein the isolation layer on the semiconductor strip has a thicker thickness than on the isolation dielectric.

10. The method of claim 5 , wherein the isolation layer has a first portion embedded in the one of the source/drain structures.

11. The method of claim 10 , wherein the one of the source/drain structures is in a position higher than a bottom surface of the first portion of the isolation layer.

12. The method of claim 10 , wherein the first portion of the isolation layer underlying the one of the source/drain structures has a narrower width than a second portion of the isolation layer underlying the gate structure along a lengthwise direction of the gate structure.

13. The method of claim 5 , wherein the isolation layer is in direct contact with the source/drain structures.

14. The method of claim 5 , wherein the step of forming the isolation layer is performed after the step of forming the source/drain structures and prior to the step of forming the gate structure.

15. A method for forming a semiconductor device, comprising: forming a semiconductor strip extending upwardly from a substrate; forming a sacrificial layer over the semiconductor strip; forming a stack of alternating first and second semiconductor layers over the sacrificial layer; forming an isolation dielectric laterally surrounding the semiconductor strip; forming a hard mask layer extending across the stack and the sacrificial layer, such that the hard mask layer has a first portion wrapping around the stack, a second portion on a sidewall of the sacrificial layer, and a third portion extending on a top surface of the isolation dielectric; forming a dummy gate structure over the hard mask layer and extending across the stack and the sacrificial layer; forming a pair of source/drain structures over the semiconductor strip and on opposite sides of the stack; patterning the dummy gate structure to form an opening exposing the third portion of the hard mask layer, wherein from a top view, the opening does not overlap the stack; removing the second and third portions of the hard mask layer through the opening to expose the sidewall of the sacrificial layer; removing the sacrificial layer through the opening to form a first space between the semiconductor strip and the stack and a second space between the semiconductor strip and one of the source/drain structures; forming an isolation layer having a first portion in the first space and interposing the semiconductor strip and the stack, and a second portion in the second space and interposing the semiconductor strip and the one of the source/drain structures through the opening; after forming the isolation layer, removing the patterned dummy gate structure, the first portion of the hard mask layer, and the first semiconductor layers; and forming a gate structure surrounding each of the second semiconductor layers.

16. The method of claim 15 , wherein the one of the source/drain structures is spaced apart from the semiconductor strip by the second portion of the isolation layer.

17. The method of claim 15 , wherein the one of the source/drain structures wraps around three sides of the second portion of the isolation layer.

18. The method of claim 15 , wherein the isolation layer has a width substantially the same as a width of the semiconductor strip along a lengthwise direction of the gate structure.

19. The method of claim 15 , further comprising: forming isolation dielectric laterally surrounding the semiconductor strip, wherein the step of forming the isolation layer is performed such that the first portion of the isolation layer is further formed on the isolation dielectric.

20. The method of claim 19 , wherein the second portion of the isolation layer on the semiconductor strip has a thicker thickness than on the isolation dielectric.

10074575 September 2018 Guillorn
10840329 November 2020 Xie
2021/0226034 July 2021 Xie
2023/0060619 March 2023 Frougier
2023/0133545 May 2023 Frougier

S. Kal et al., “Selective isotropic etching of Group IV semiconductors to enable gate all around device architectures”, TEL Technology Center, America, LLC-imec , Apr. 10, 2018. cited by applicant
Akihiro Kojima et al., “Dual-Frequency Superimposed RF Capacitive-Coupled Plasma Etch Process”, Japanese Journal of Applied Physics, vol. 44, No. 8, 2005. cited by applicant
B. E. E. Kastenmeier et al., “Highly selective etching of silicon nitride over silicon and silicon dioxide”, Journal of Vacuum Science & Technology A, 1999. cited by applicant
C. Auth et al., “A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors”, Symposium on VLSI Technology Digest of Technical Papers, 2012. cited by applicant
G. Dingemans et al., “Plasma-Assisted ALD for the Conformal Deposition of SiO2: Process, Material and Electronic Properties”, Journal of The Electrochemical Society, 2012. cited by applicant
Geumjong Bae et al., “3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications”, IEEE, 2018. cited by applicant
H. Arimura et al., “A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation”, Symposium on VLSI Technology Digest of Technical Papers, 2019. cited by applicant
H. Mertens et al., “Vertically Stacked Gate-All-Around Si Nanowire Transistors: Key Process Optimizations and Ring Oscillator Demonstration”, IEDM, 2017. cited by applicant
L. Witters et al., “Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition”, IEEE Transactions on Electron Devices, vol. 64, No. 11, Nov. 2017. cited by applicant
M. Garcia Bardon et al., “Extreme Scaling enabled by 5 Tracks Cells : Holistic design-device co-optimization for FinFETs and Lateral Nanowires”, IEDM, 2016. cited by applicant
M.J.H. van Dal et al., “Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs”, IEDM, 2018. cited by applicant
Nicolas Loubet et al., “Selective etching of Si1-xGex versus Si with gaseous HCI for the formation of advanced CMOS devices”, Thin Solid Films, 2008. cited by applicant
N. Loubet et al., “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET”, Symposium on VLSI Technology Digest of Technical Papers, 2017. cited by applicant
F. Roozeboom et al., “Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching”, ECS Journal of Solid State Science and Technology, 2015. cited by applicant
Stephan Borel et al., “Control of Selectivity between SiGe and Si in Isotropic Etching Processes”, Japanese Journal of Applied Physics, 2004. cited by applicant
S.C. Song et al., “2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices”, Symposium on VLSI Technology Digest of Technical Papers, 2019. cited by applicant
T. Tastsumi et al., “Quantitative control of etching reactions on various SiOCH materials”, Journal of Vacuum Science & Technology A, 2005. cited by applicant
Y. Bogumilowicz et al., “Chemical vapour etching of Si, SiGe and Ge with HCI; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations”, Semiconductor Science and Technology, 2005. cited by applicant
Y.M. Lee et al., “Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology”, IEDM, 2017. cited by applicant

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